`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    13:17:45 05/25/2012 
// Design Name: 
// Module Name:    Convector 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Convector(
		input wire systemclock,
		input wire reset,
		input wire coderConvEn,
		input wire [16:0] coderConvData,

		output reg convFifoWrite,
		output reg [7:0] convFifoData,
		output reg 	ConvTestFlag
    );
	 
reg [16:0] DataIn;
reg [2:0] Cnt;
reg       ConvFlag;

parameter BCD_1 = 3'd1,
			 BCD_2 = 3'd2,
			 BCD_3 = 3'd3,
			 BCD_4 = 3'd4,
			 dot_5 = 3'd5,
			 enter_6 = 3'd6;


always@(posedge systemclock)
	if(reset)
		begin
			convFifoWrite =0;
			convFifoData	=8'h00;
			Cnt 			=0;
			ConvFlag		=0;
			ConvTestFlag =0;
			end
	else if(coderConvEn)begin
			ConvTestFlag=1;
			DataIn=coderConvData;
			Cnt =0;
			ConvFlag = 1;
			end
	else begin
			if(ConvFlag)
			case(Cnt)
				3'd0:if(DataIn[16])begin
						convFifoData=8'd45;
						convFifoWrite=1'b1;
						Cnt=BCD_1;
						end
						else begin
						convFifoWrite =0;
						Cnt=BCD_1;
						end
				BCD_1:begin
						convFifoData=8'd48+DataIn[15:12];
						convFifoWrite=1'b1;
						Cnt=BCD_2;
						end
				BCD_2:begin
						convFifoData=8'd48+DataIn[11:8];
						convFifoWrite=1'b1;
						Cnt=dot_5;
						end
				dot_5:begin
						convFifoData=8'd46;
						convFifoWrite=1'b1;
						Cnt=BCD_3;
						end
				BCD_3:begin
						convFifoData=8'd48+DataIn[7:4];
						convFifoWrite=1'b1;
						Cnt=BCD_4;
						end
				BCD_4:begin
						convFifoData=8'd48+DataIn[3:0];
						convFifoWrite=1'b1;
						Cnt=enter_6;
						end
				enter_6:begin
						convFifoData=8'd10;
						convFifoWrite=1'b1;
						Cnt=0;
						ConvFlag=0;
						end
		endcase
		else convFifoWrite =0;
	end

endmodule
